Hardware-efficient VLSI design for cascade support vector machine with on-chip training and classification capability

Journal article

Merin Loukrakpam, Madhuchhanda Choudhury
Circuits, Systems, and Signal Processing, vol. 39, Springer US, 2020, pp. 5272--5297

Cite

APA Click to copy
Loukrakpam, M., & Choudhury, M. (2020). Hardware-efficient VLSI design for cascade support vector machine with on-chip training and classification capability. Circuits, Systems, and Signal Processing, 39, 5272–5297.

Chicago/Turabian Click to copy
Loukrakpam, Merin, and Madhuchhanda Choudhury. “Hardware-Efficient VLSI Design for Cascade Support Vector Machine with on-Chip Training and Classification Capability.” Circuits, Systems, and Signal Processing 39 (2020): 5272–5297.

MLA Click to copy
Loukrakpam, Merin, and Madhuchhanda Choudhury. “Hardware-Efficient VLSI Design for Cascade Support Vector Machine with on-Chip Training and Classification Capability.” Circuits, Systems, and Signal Processing, vol. 39, Springer US, 2020, pp. 5272–97.

BibTeX Click to copy

@article{loukrakpam2020a,
  title = {Hardware-efficient VLSI design for cascade support vector machine with on-chip training and classification capability},
  year = {2020},
  journal = {Circuits, Systems, and Signal Processing},
  pages = {5272--5297},
  publisher = {Springer US},
  volume = {39},
  author = {Loukrakpam, Merin and Choudhury, Madhuchhanda}
}